Method of manufacturing semiconductor device using plasma doping process and semiconductor device manufactured by the method

ABSTRACT

A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application is a continuationapplication of and claims priority to U.S. patent application Ser. No.14/460,404 filed on Aug. 15, 2014, which claims priority under 35 U.S.C.§119 to Korean Patent Application No. 10-2013-0138426, filed on Nov. 14,2013 in the Korean Intellectual Property Office (KIPO), the contents ofeach of which are herein incorporated by reference in their entirety.

BACKGROUND

Nowadays, semiconductor devices are very widely used in electronicindustries because they have many beneficial characteristics, such as apossibility of miniaturization, a multi-functional ability, and a lowermanufacturing cost, etc. These semiconductor devices include memorydevices, logic devices, and/or hybrid devices performing variousfunctions simultaneously.

In response to the growing demands for miniaturized semiconductordevices, the pattern size of semiconductor devices has become muchsmaller. If the pattern size is very small, process margins formanufacturing these semiconductor devices should be reduced. Thus, it isbecoming very difficult to form the smaller patterns due to the reducedprocess margin, such as an exposure margin of a photolithographicprocess.

In addition, demands for forming a high-speed semiconductor device arealso increasing. Therefore, various studies have been conducted to meetthe demands for forming miniaturized semiconductor devices andhigh-speed semiconductor devices.

Certain semiconductor devices include fin structures, such as fin FieldEffect Transistors (FinFETS). Methods of manufacturing these finstructures have included doping using plasma processes. See, e.g., U.S.Pat. Nos. 8,409,939, 8,298,925, and 8,124,507, each of which isincorporated herein in its entirety by reference.

SUMMARY

An aspect of the present inventive concepts provides a method ofmanufacturing a semiconductor device using a using a plasma dopingprocess and a semiconductor device manufactured by the method. Thesemiconductor device may have a fin-type field effect transistor(FinFET).

In one example embodiment, the method may include forming a preliminaryfin-type active pattern by partially etching a substrate, thepreliminary fin-type active pattern extending in a first direction,forming a device isolation pattern covering a lower portion of thepreliminary fin-type active pattern, forming a gate structure crossingover the preliminary fin-type active pattern, the gate structureextending in a second direction and the preliminary fin-type activepattern having an exposed upper portion not covered by the gatestructure, forming a fin-type active pattern having a first region and asecond region by etching the exposed upper portion of the preliminaryfin-type active pattern, the first region being located below the gatestructure and the second region being located at both sides of the gatestructure wherein the first region has sidewall surfaces and the secondregion has upper surfaces, forming an impurity-doped region at thesidewall surfaces of the first region and at the upper surface of thesecond region by using a plasma doping process, and forming animpurity-doped pattern on the second region by using a selectiveepitaxial-growth process, wherein an upper surface of the first regionis at a first level and an upper surface of the second region is at asecond level lower than the first level.

The method may further include annealing the substrate after the plasmadoping process, and wherein the impurity-doped region has substantiallythe same thickness at the sidewall surfaces of the first region and atthe upper surface of the second region.

The impurity-doped region may have a substantially uniform thicknessalong the sidewall surfaces of the first region and along the uppersurfaces of the second region.

The method of annealing the substrate may include performing a firstheat treatment to the impurity-doped region at a first temperature, andperforming a second heat treatment to the impurity-doped region at asecond temperature higher than the first temperature.

The first heat treatment may include at least one selected from thegroup consisting of a rapid thermal anneal (RTA), a rapid thermaloxidation, a plasma annealing, and a microwave annealing.

The second heat treatment may include at least one selected from thegroup consisting of a spike RTA, a flash RTA, and a laser annealing.

The plasma doping process may include supplying an impurity gas to thesubstrate, forming a plasma in order to ionize impurities of theimpurity gas, and injecting the ionized impurities into the sidewalls ofthe first region and the upper surfaces of the second region bysupplying a bias voltage to the substrate.

The impurity gas may include boron (B).

The impurity gas may further include carbon (C).

The impurity-doped pattern may have a compressive stress.

The impurity gas may include at least one selected from the groupconsisting of arsenic (As) and phosphorus (P).

The impurity-doped pattern may have a tensile stress.

The plasma doping process may further include supplying a dilution gasto the substrate.

The dilution gas may include at least one element selected from thegroup consisting of argon (Ar), neon (Ne), helium (He), hydrogen (H),Krypton (Kr), and Xenon (Xe).

The method may further include removing the impurity-doped region formedat the upper surfaces of the second region.

The method of forming the impurity-doped pattern may further includesupplying at least one impurity to the impurity-doped pattern by usingan in-situ process during the selective epitaxial-growth process.

The method may further include removing a by-product formed during theplasma doping process.

The method may further include forming a passivation layer on theimpurity doped region after the plasma doping process.

The method of forming the passivation layer may include supplying anoxygen-plasma to the impurity-doped region.

The method may further include performing a knock-in process after theplasma doping process. The knock-in process may be performed by using atleast one selected from the group consisting of argon (Ar), neon (Ne),helium (He), hydrogen (H), Krypton (Kr), and Xenon (Xe).

The method of forming the gate structure may include formingsequentially a dielectric layer and a material layer on the preliminaryfin-type active pattern, forming a mask pattern extending in the seconddirection on the material layer, forming a line pattern and a dielectriclayer pattern by etching the material layer and the dielectric layerusing the mask pattern as an etch mask, and forming a spacer on thesidewall of the line pattern and the dielectric layer pattern.

The method may further include forming a trench by removing a portion ofthe gate structure in order to expose a portion of the device isolationpattern and the first region of the fin-type active pattern, conformallyforming a dielectric layer pattern on the device isolation pattern andthe first region exposed in the trench, and forming a gate electrodefilling the trench on the dielectric layer pattern.

In another example embodiment, a method of manufacturing a semiconductordevice includes: providing a substrate; forming a fin-type activepattern on the substrate, the fin-type active pattern extending in afirst direction and having a first portion and a second portion, whereinthe first portion extends upwards from the second portion and hassidewall surfaces, and an upper surface of the first portion is at afirst level and an upper surface of the second portion is at a secondlevel lower than the first level; forming a device isolation patterncovering a lower portion of the fin-type active pattern; forming a gatestructure crossing over the fin-type active pattern, the gate structureextending in a second direction perpendicular to the first direction,wherein the first portion is located below the gate structure and thesecond portion is located at both sides of the gate structure; andforming an impurity-doped region at sidewall surfaces of the firstportion and at upper surfaces of the second portion by using a plasmadoping process. The impurity-doped region has substantially the same anduniform thickness along the sidewall surfaces of the first region andalong the upper surfaces of the second region.

The method may additionally include forming an impurity-doped pattern onthe second region by using a selective epitaxial-growth process.

In one embodiment, widths of individual impurity doping bands of theimpurity-doped pattern are substantially uniform.

The plasma doping process may further include supplying an impurity gasto the substrate; forming a plasma in order to ionize impurities in theimpurity gas; and injecting the ionized impurities into the sidewalls ofthe first region and the upper surfaces of the second region bysupplying a bias voltage to the substrate.

Forming the gate structure may further include forming sequentially adielectric layer and a material layer on a preliminary fin-type activepattern; forming a mask pattern extending in the second direction on thematerial layer; forming a line pattern and a dielectric layer pattern byetching the material layer and the dielectric layer using the maskpattern as an etch mask; and forming a spacer on the sidewall of theline pattern and the dielectric layer pattern.

In another example embodiment of the inventive concepts, a method ofmanufacturing a semiconductor device may include forming a preliminaryfin-type active pattern by partially etching a substrate, thepreliminary fin-type active pattern extending in a first direction,forming a device isolation pattern covering a lower portion of thepreliminary fin-type active pattern, forming a pattern structurecrossing over the preliminary fin-type active pattern, the patternstructure extending in a second direction and the preliminary fin-typeactive pattern having an exposed upper portion not covered by thepattern structure, forming a fin-type active pattern having a firstregion and a second region by etching the exposed upper portion of thepreliminary fin-type active pattern, the first region being locatedbelow the pattern structure and having an upper surface, and the secondregion being located at both sides of the pattern structure and havingan upper surface, forming a preliminary impurity-doped pattern on thesecond region by using a selective epitaxial-growth process, and formingan impurity-doped pattern from the preliminary impurity-doped pattern byinjecting impurities using a plasma doping process, wherein the uppersurface of the first region is at a first level and the upper surface ofthe second region is at a second level lower than the first level.

The method may further include annealing the impurity-doped patternafter the plasma doping process.

The method of annealing the impurity-doped pattern may include at leastone selected from the group consisting of a spike RTA, a flash RTA, anda laser annealing.

The method may further include performing an ion beam doping process toinject impurities into the impurity-doped pattern.

In still another example embodiment of the inventive concepts, asemiconductor device may include a fin-type active pattern protrudingfrom a substrate and extending in a first direction, the fin-type activepattern including a first region having a first vertical thickness andhaving sidewalls and a second region having a second vertical thicknessand an upper surface, the second vertical thickness less than the firstvertical thickness, a pattern structure crossing over the first regionof the fin-type active pattern, the pattern structure extending in asecond direction, and an impurity-doped pattern having an impurityconcentration on the second region of the fin-type active pattern,wherein the impurity concentration of the impurity-doped pattern alongthe sidewall of the first region is substantially uniform.

The semiconductor device may further include a device isolation patterncovering a lower portion of the fin-type active pattern, wherein theupper surface of the first region is higher than the upper surface ofthe device isolation pattern, and wherein the upper surface of thesecond region is lower than the upper surface of the device isolationpattern.

The upper surface of the impurity-doped pattern may be higher than theupper surface of the device isolation pattern, but lower than the uppersurface of the pattern structure.

A sidewall of the impurity-doped pattern may have an impurityconcentration higher than an impurity concentration at the bottom of theimpurity-doped pattern.

The sidewalls of the first region may have an impurity concentrationhigher than that of the upper surface of the second region.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features and advantages of this disclosure willbe apparent from the more particular description of the exampleembodiments, as illustrated in the accompanying drawings in which likereference characters refer to the same parts throughout the differentviews. The drawings are not necessarily to scale, emphasis instead beingplaced upon illustrating the principles of the disclosed embodiments.

FIGS. 1a through 1d are a perspective view and cross-sectional viewsillustrating a semiconductor device according to an example embodimentof the inventive concepts.

FIGS. 2a through 2d are a perspective view and cross-sectional viewsillustrating a semiconductor device according to another exampleembodiment of the inventive concepts.

FIGS. 3a through 10a are perspective views illustrating a method ofmanufacturing a semiconductor device according to an example embodimentof the inventive concepts.

FIGS. 3b through 10b are cross-sectional views illustrating a method ofmanufacturing a semiconductor device according to an example embodimentof the inventive concepts corresponding to line I-I′ of FIG. 10 a.

FIGS. 1a through 20a are perspective views illustrating a method ofmanufacturing a semiconductor device according to an example embodimentof the inventive concepts.

FIGS. 11b through 20b are cross-sectional views illustrating a method ofmanufacturing a semiconductor device according to an example embodimentof the inventive concepts corresponding to line I-II′ of FIG. 20 a.

FIGS. 21a through 25a are perspective views illustrating a method ofmanufacturing a semiconductor device according to an example embodimentof the inventive concepts.

FIGS. 21b through 25b are cross-sectional views illustrating a method ofmanufacturing a semiconductor device according to an example embodimentof the inventive concepts corresponding to line I-II′ of FIGS. 21athrough 25 a.

FIG. 26a is a cross-sectional view illustrating a distribution ofimpurity concentration in an impurity-doped pattern of a conventionalfin-type field effect transistor.

FIG. 26b is a cross-sectional view illustrating a distribution ofimpurity concentration in an impurity-doped pattern of a fin-type fieldeffect transistor manufactured according to an example embodiment of theinventive concepts.

FIG. 27a is a schematic block diagram illustrating a memory cardincluding a semiconductor device according to an example embodiment ofthe inventive concepts.

FIG. 27b is a schematic block diagram illustrating an example ofinformation processing systems including a semiconductor deviceaccording to an example embodiment of the inventive concepts.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments will now be described more fully hereinafter withreference to the accompanying drawings; however, they may be embodied indifferent forms and should not be construed as limited to the exampleembodiments set forth herein.

As used herein, the term “and/or” includes any and all combinations ofone or more of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, or “contacting”another element, there are no intervening elements present. Other wordsused to describe the relationship between elements or layers should beinterpreted in a like fashion (e.g., “between” versus “directlybetween,” “adjacent” versus “directly adjacent,” “on” versus “directlyon,” “under” versus “directly under”).

It will be understood that, although the terms “first”, “second”, etc.,may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. Unless the contextindicates otherwise, these terms are only used to distinguish oneelement, component, region, layer or section from another element,component, region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of example embodiments.

In the drawings, the dimensions of layers and regions may be exaggeratedfor clarity of illustration. Like reference numerals refer to likeelements throughout the specification.

Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe the relationship of one element or feature to anotherelement(s) or feature(s), as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. For example, if the device inthe figures is turned over, elements described as “below” or “beneath”other elements or features would then be oriented “above” the otherelements or features. Thus, the exemplary term “below” can encompassboth an orientation of above and below. The device may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein interpreted accordingly.

The use of the terms “a” and “an” and “the” and similar referents in thecontext of describing embodiments (especially in the context of thefollowing claims) are to be construed to cover both the singular and theplural, unless otherwise indicated herein or clearly contradicted bycontext. The terms “comprising,” “having,” “including,” and “containing”are to be construed as open-ended terms (i.e., meaning “including, butnot limited to”) unless otherwise noted.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art. It is noted that the use of any and all examples, or exemplaryterms provided herein is intended merely to better illuminate theexample embodiments and is not a limitation on the scope of theinventive concepts unless otherwise specified.

Example embodiments will be described with reference to perspectiveviews, cross-sectional views, and/or plan views. The profile of anexample view may be modified according to, e.g., manufacturingtechniques and/or allowances. Accordingly, the example embodiments arenot intended to limit the scope, but cover all changes and modificationsthat can be caused due to, e.g., a change in manufacturing process.Thus, regions shown in the drawings are illustrated in schematic formand the shapes of the region are presented simply by way of illustrationand not as a limitation.

Hereinafter, example embodiments of the inventive concepts will bedescribed in detail with reference to the accompanying drawings.

FIG. 1a is a perspective view illustrating a semiconductor deviceaccording to an example embodiment of the inventive concepts. FIG. 1b isa cross-sectional view illustrating a semiconductor device correspondingto line I-I′ of FIG. 1a . FIG. 1c is a cross-sectional view illustratinga semiconductor device corresponding to line II-II′ of FIG. 1a . FIG. 1dis a cross-sectional view illustrating a semiconductor devicecorresponding to line III-III′ of FIG. 1 a.

Referring to FIGS. 1a through 1d , a semiconductor device includes asubstrate 100, a fin-type active pattern 122, a device isolation pattern106, a pattern structure 120, a first impurity-doped pattern 132 a, anda second impurity-doped pattern 132 b.

In certain embodiments, the substrate 100 may comprise a bulk siliconsubstrate or a silicon-on-insulator (SOI) substrate. For example, thesubstrate 100 may include silicon (Si), silicon germanium (SiGe), indiumantimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indiumphosphide (InP), gallium arsenide (GaAs), and/or gallium antimonide(GaSb). The substrate 100 may also include an epitaxial layer formed ona base substrate.

The fin-type active pattern 122 may extend in a first direction. Forexample, the first direction may be along an X-axis. The fin-type activepattern 122 may include a plurality of patterns. The plurality of thefin-type active patterns may be extended to the first direction andspaced from each other substantially the same distance to a seconddirection. For example, the second direction may be along a Y-axis. Thefin-type active pattern 122 may be a part of the substrate 100. In oneembodiment, for example, the fin-type active pattern 122 includes anepitaxial layer grown from the substrate 100.

The fin-type active pattern 122 may protrude from the substrate in athird direction. For example, the third direction may be along a Z-axis(e.g., vertically). In one embodiment, the fin-type active pattern 122has a first portion 122 a formed in a first active pattern region and asecond portion 122 b formed in a second active pattern region, bothportions protruding from the substrate 100. The first portion 122 a,also explained herein as a first region 122 a, may have a firstthickness ACT_D1 from the substrate 100 and the second portion 122 b,also explained herein as a second region 122 b may have a secondthickness ACT_D2 from the substrate 100. The second thickness ACT_D2 maybe less than the first thickness ACT_D1. The second region 122 b may bedisposed at both sides of the first region 122 a. The first portion 122a and second portion 122 b may form an upside-down T-shape. For example,the first portion 122 a may include the entire section of the fin-typeactive pattern 122 whose vertical thickness is depicted as ACT_D1 orgreater, and the second portion 122 b may include the remaining sectionof the fin-type active pattern 122 whose vertical thickness is depictedas ACT-D2. A first and a second impurity-doped region 132 a and 132 bare disposed in the second active pattern region on the second portion122 b which is disposed at the both sides of the first active patternregion.

The device isolation pattern 106 may cover a lower portion of thesidewalls of the fin-type active pattern 122. For example, the deviceisolation pattern 106 may cover a lower portion of the first region 122a of the fin-type active pattern 122. The upper surface of the firstregion 122 a may be at a level higher than that of the upper surface ofthe device isolation pattern 106. On the contrary, the upper surface ofthe second region 122 b of the fin-type active pattern may be at a levelequal to or lower than that of the upper surface of the device isolationpattern 106. The device isolation pattern 106 may comprise, for example,silicon oxide, silicon nitride, and/or silicon oxynitride.

The pattern structure 120 may include an insulation pattern 112, a linepattern 114, and/or a spacer 116. The line pattern 114 may have a lineshape, for example, crossing over the fin-type active pattern 122. Forexample, the line pattern 114 may be extended along the Y-axis. Thoughonly one line is shown, the line pattern 114 may comprise a plurality oflines. The plurality of lines of the line pattern 114 may be spaced fromeach other by substantially the same distance in the X-direction. Incertain embodiments, the line pattern 114 may be a portion of a gateelectrode of a fin-type field effect transistor (FinFET). For example,the line pattern may include a conductive material that forms the gateelectrode. The pattern structure 120 may therefore include a pluralityof gate structures extending in the Y-direction and separated from eachother in the X-direction.

The line pattern 114 may cover the device isolation pattern 106 and aportion of the first region 122 a of the fin-type active pattern 122.The line pattern 114 may comprise a first region 114 a having a firstthickness CP_D1 and a second region 114 b having a second thicknessCP_D2. Note that the term “pattern” as used herein may refer to a groupof repeated elements or single element. For example, a line pattern asdescribed herein may refer to a single line, or to a group of linesspaced apart from each other that are formed by the same patterningprocess. The first region 114 a of the line pattern 114 may be disposedon the first region 122 a of the fin-type active pattern 122. The secondregion 114 b of the line pattern 114 may be disposed on the deviceisolation pattern 106. The upper surfaces of the first region 114 a ofthe line pattern 114 may have a level substantially equal to that of theupper surface of the second region 114 b of the line pattern 114. Theline pattern 114 may cover the upper surface and the sidewall of thefirst region 122 a of the fin-type active pattern 122. In oneembodiment, the insulation pattern 112 is disposed between the firstregion 122 a of the fin-type active pattern 122 and the line pattern 114as shown in FIG. 1 d.

The line pattern 114 may include, for example, silicon (Si) or silicongermanium (SiGe). The line pattern 114 may also include a metal or ametal compound. For example, the line pattern 114 may include at leastone selected from the group consisting of tungsten (W), aluminum (Al),titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC),tantalum carbide (TaC).

The insulation pattern 112, which is disposed between the first region122 a of the fin-type active pattern 122 and the line pattern 114, mayextend along the Y-axis direction. The insulation pattern 112 mayperform as a gate dielectric layer of the fin-type field effecttransistor (FinFET). The insulation pattern 112 may include, forexample, silicon oxide (SixOy). The insulation pattern 112 may alsoinclude a high-k dielectric layer having a higher dielectric constantthan that of a silicon oxide layer. For example, the insulation pattern112 may include at least one selected from the group consisting ofhafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanumaluminum oxide, zirconium oxide, zirconium silicon oxide, tantalumoxide, titanium oxide, barium strontium titanium oxide, barium titaniumoxide, strontium titanium oxide, yttrium oxide, aluminum oxide, leadscandium tantalum oxide, or lead zinc niobate.

The spacer 116 may be disposed at the sidewalls of the insulationpattern 112 and the line pattern 114 and may extend along the Y-axisdirection. The spacer 116 may include, for example, silicon nitride,silicon oxide, and/or silicon oxynitride.

The spacer 116 may comprise a first region 116 a having a firstthickness SP_D1 (also described as a first height) and a second region116 b having a second thickness SP_D2 (also described as a secondheight) thicker or greater than the first thickness SP_D1. The firstregion 116 a of the spacer 116 may be disposed on the first region 112 aof the fin-type active pattern 122. The second region 116 b of thespacer 116 may be disposed on the device isolation pattern 106. Theuppermost surfaces of the first and second regions 116 a and 116 b ofthe spacer 116 may be at substantially the same level. A lower portionof the sidewall of the spacer 116 and the uppermost portion of thesidewall of the first region 122 a of the fin-type active pattern 122may be at substantially the same level as shown in FIG. 1b . Thus, thesesidewalls may have overlapping heights in the Z-direction. Thus, thesidewall of the first region 122 a of the fin-type active pattern 122may be exposed in relation to the substrate at the bottom of the spacer116.

The pattern structure 120 may include a mask pattern 110 disposed on theline pattern 114. The mask pattern 110 may also extend in the Y-axisdirection. The mask pattern 110 may include, for example, siliconnitride and/or silicon oxynitride.

The first and second impurity-doped patterns 132 a and 132 b may bedisposed on the second region 122 b of the fin-type active pattern 122.At least one of n-type or p-type Impurities may be injected into thefirst and second impurity-doped patterns 132 a and 132 b, for example,by a plasma doping process. The impurity concentration along thesidewall of the first impurity-doped pattern 132 a may be substantiallythe same as the impurity concentration along the sidewall the secondimpurity-doped pattern 132 b. In addition, the impurity concentration ofeach of these impurity-doped patterns may be uniform along thesesidewalls. The impurity concentration of each of the first and secondimpurity-doped patterns 132 a and 132 b at the sidewall of the firstregion 122 a of the fin-type active pattern 122 may also besubstantially the same along the Z-axis direction and may further beuniform along these sidewalls.

In one embodiment, the first and the second impurity-doped pattern 132 aand 132 b may be formed on the second region 122 b of the fin-typeactive pattern 122 by using a selective epitaxial growth (SEG) process.Therefore, a vertical plane of the first and the second impurity-dopedpattern 132 a and 132 b may have a circle shape or a polygonal shape. Ahorizontal width of the first and the second impurity-doped pattern 132a and 132 b (e.g., along a Y-axis direction) may be greater than that ofthe second region 122 b of the fin-type active pattern 122. The uppersurfaces of the first and second impurity-doped patterns 132 a and 132 bmay be at a level higher than that of the upper surface of the deviceisolation pattern 106, but lower than that of the upper surface of thepattern structure 120. However, in certain embodiments, the first andsecond impurity-doped patterns 132 a and 132 b may have a differentshape unlike mentioned above.

If the semiconductor device includes a fin-type PMOS transistor, thefirst and second impurity-doped patterns 132 a and 132 b may have acompressive stress. The compressive stress may be induced, for example,by injecting a material having a lattice constant greater than that ofsilicon (Si), e.g., silicon germanium (SiGe) into the first and secondimpurity-doped patterns 132 a and 132 b. The compressive stress inducedin the first and second impurity-doped patterns 132 a and 132 b mayincrease the carrier mobility in the channel area of the fin-type PMOStransistor. The first and second impurity-doped patterns 132 a and 132 bmay include, for example, boron (B). The first and second impurity-dopedpatterns 132 a and 132 b may further include carbon (C) in order toprevent or decrease diffusion of the boron.

If the semiconductor device includes a fin-type NMOS transistor, thefirst and second impurity-doped patterns 132 a and 132 b may have atensile stress. The tensile stress may be induced by injecting amaterial having a lattice constant less than that of silicon (Si), e.g.,silicon carbide (SiC) into the first and second impurity-doped patterns132 a and 132 b. The tensile stress induced in the first and secondimpurity-doped patterns 132 a and 132 b may increase the carriermobility in the channel area of the fin-type NMOS transistor. The firstand second impurity-doped patterns 132 a and 132 b may include, forexample, phosphorus (P) and/or arsenic (As).

In certain embodiments, the sidewall of the first and secondimpurity-doped pattern 132 a and 132 b (e.g., a sidewall on an outsideof a first active pattern region 122 a of the pattern structure 120) mayhave an impurity concentration higher than that of the bottom of thefirst and second impurity-doped pattern 132 a and 132 b (e.g., theportions of the first and second impurity-doped patterns 132 a and 132 bbelow a top surface of the device isolation pattern 106, such as abottom surface of the first and second impurity-doped patterns 132 a and132 b).

The first and second impurity-doped pattern 132 a and 132 b may have alightly doped drain (LDD) structure. Portions of the first and secondimpurity-doped patterns 132 a and 132 b adjacent to the first region 122a of the fin-type active pattern 122 (e.g., directly adjacent to and/orcontacting the first region 122 a) may have impurity concentrationslower than those of the other portions of the first and secondimpurity-doped patterns 132 a and 132 b, respectively.

The upper surfaces of the first and second impurity-doped patterns 132 aand 132 b may have an impurity concentration higher than that of certainother portions of the first and second impurity-doped patterns 132 a and132 b (e.g., portions below the upper surfaces). Thus, contactresistances which are formed between the upper surfaces of the first andsecond impurity-doped patterns 132 a and 132 b and contact plugs beingelectrically connected to them, may become lower.

When the impurities are injected into the first and secondimpurity-doped patterns 132 a and 132 b by using a plasma dopingprocess, the source/drain junction depth of the fin-type field effecttransistor (FinFET) is controlled uniformly and the transistor'sperformance of the semiconductor device is improved.

FIG. 2a is a perspective view illustrating a semiconductor deviceaccording to another example embodiment of the inventive concepts. FIG.2b is a cross sectional view illustrating a semiconductor devicecorresponding to line I-I′ of FIG. 2a . FIG. 2c is a cross sectionalview corresponding to line II-II′ of FIG. 2a . FIG. 2d is a crosssectional view corresponding to line III-III′ of FIG. 2 a.

Referring to FIGS. 2a through 2d , a semiconductor device may include asubstrate 100, a fin-type active pattern 122, a device isolation pattern106, a pattern structure 250, a first impurity-doped pattern 220 a, anda second impurity-doped pattern 220 b.

The pattern structure 250 may include a gate dielectric layer pattern240, a gate electrode 242, and a spacer 116.

The gate electrode 242 may have a line shape crossing over the fin-typeactive pattern 122. For example, the gate electrode 242 may extend inthe Y-axis direction. The gate electrode 242 may be formed by using areplacement process including removing the line pattern 114 as mentionedabove referring to FIGS. 1a through 1 d.

The gate electrode 242 may have a multilayer structure. If the gateelectrode 242 has a structure of bilayer, a lower layer 242 a of thegate electrode 242 may control the work function value of the gateelectrode 242 and include at least one selected from the group oftitanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC),and tantalum carbide (TaC). An upper layer 242 b of the gate electrode242 may include tungsten (W) and/or aluminum (Al).

The gate dielectric layer pattern 240 may cover the sidewall and thebottom of the gate electrode 242 and may extend in the Y-axis direction.The gate dielectric layer pattern 240 may be formed by a replacementprocess including removing the insulation pattern 112 as mentioned abovereferring to FIGS. 1a through 1 d.

A detailed description about the spacer 115 may be omitted because inone embodiment, it is substantially the same to the description asmentioned above referring to FIGS. 1a and 1 b.

The semiconductor device may further include an interlayer insulatinglayer 230 covering the sidewall of the pattern structure 250. The uppersurface of the interlayer insulating layer 230 may be at substantiallythe same level as the upper surface of the pattern structure 250. Theinterlayer insulating layer 230 may include, for example, silicon oxide,silicon nitride, and/or silicon oxynitride.

Detailed descriptions about the substrate 100, the fin-type activepattern 122, the device isolation pattern 106, the pattern structure120, and the first and second impurity-doped patterns 220 a and 220 bare also omitted because they may be substantially the same as thedescriptions as mentioned above referring to FIGS. 1a through 1 d.

FIGS. 3a through 10a are perspective views illustrating a method ofmanufacturing a semiconductor device according to still another exampleembodiment of the inventive concepts. FIGS. 3b through 10b arecross-sectional views illustrating a method of manufacturing asemiconductor device according to an example embodiment of the inventiveconcepts corresponding to line I-I′ of FIG. 10 a.

Referring to FIGS. 3a and 3b , one or more trenches 104 extending alongthe X-axis direction and defining a plurality of preliminary fin-typeactive patterns 102 may be formed by etching the substrate 100 using afirst mask pattern. The plurality of the preliminary fin-type activepatterns 102 are separated from each other in the Y-axis direction. Eachmay be defined by two trenches 104 and spaced from an adjacentpreliminary fin-type active pattern 102 by a particular distance.

Referring to FIGS. 4a and 4b , a device isolation pattern 106 may beformed in the trench 104. Specifically, a device isolation layer fillingthe trench 104 may be formed on the substrate 100 and the plurality ofthe preliminary fin-type active patterns 102. The device isolation layermay include, for example, silicon oxide, silicon nitride, and/or siliconoxynitride. The device isolation layer may be planarized by aplanarization process. In one embodiment, after planarization, the uppersurface of the device isolation layer is at substantially the same levelas the upper surfaces of the plurality of the preliminary fin-typeactive patterns 102. And then, the device isolation layer may berecessed, for example, using an etch-back process to form the deviceisolation pattern 106. Upper sidewalls of the plurality of thepreliminary fin-type active patterns 102 (e.g., sidewalls extendingalong the X-Z plane, and also sidewalls extending along the Y-Z plane)may be exposed after the etch-back process.

In an alternative embodiment, an epitaxial layer may be formed on theplurality of the preliminary fin-type active patterns 102 by using anepitaxial growth process without recessing the device isolation layer106. Therefore, the epitaxial layer may extend from the upper surface ofthe substrate 100. An upper surface of the epitaxial layer may be at alevel higher than an upper surface of the device isolation layer 106.

Impurities may be injected into the plurality of the preliminaryfin-type active patterns 102 to control the threshold voltage of thefin-type field effect transistor. If the fin-type field effecttransistor is a NMOS transistor, the impurities may include, forexample, boron (B). If the fin-type field effect transistor is a PMOStransistor, the impurities may include, for example, phosphorus (P) orarsenic (As).

Referring to FIGS. 5a and 5b , an insulation pattern 112 and a linepattern 114 may be formed on the plurality of the preliminary fin-typeactive patterns 102 and the device isolation pattern 106.

Specifically, a dielectric layer and a material layer may be formed onthe plurality of the preliminary fin-type active patterns 102 and thedevice isolation pattern 106. The dielectric layer may include, forexample, silicon oxide, silicon nitride and/or silicon oxynitride. Thematerial layer may include, for example, silicon (Si) or silicongermanium (SiGe). Alternatively, the material layer may include at leastone material selected from the group consisting of tungsten (W),aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), titaniumcarbide (TiC), and tantalum carbide (TaC).

A second mask pattern 110 may be formed on the material layer. Thesecond mask pattern 110 may cross over the plurality of the preliminaryfin-type active patterns 102 and extend in the Y-axis direction.

The second mask pattern 110 may comprise a material having an etchselectivity with respect to the plurality of the preliminary fin-typeactive patterns 102. The second mask pattern 110 may include, forexample, silicon nitride, silicon oxide, and/or silicon oxynitride.Alternatively, the second mask pattern 110 may be a bilayer structurehaving a silicon nitride pattern and a photoresist pattern.

A line pattern 114 and an insulation pattern 112 which extend along theY-axis direction may be formed by etching the material layer and thedielectric layer using the second mask pattern 110 as an etch mask.

The plurality of the preliminary fin-type active patterns 102 maycomprise a first region 102 a covered by the line pattern 114 and asecond region 102 b exposed at both sides of the line pattern 114.

Referring to FIGS. 6a and 6b , a spacer 116 may be formed on thesidewalls of the insulation pattern 112 and the line pattern 114 (e.g.,on sidewalls extending along the Y-Z direction).

Specifically, a spacer layer may be conformally formed on the pluralityof the preliminary fin-type active patterns 102, the substrate 100, andthe sidewalls of the insulation pattern 112 and the line pattern 114.The spacer layer may include, for example, silicon oxide, siliconnitride, and/or silicon oxynitride. The spacer extending in the Y-axisdirection may be formed on the sidewalls of the insulation pattern 112and the line pattern 114 by etching the spacer layer using, for example,an anisotropic etching process.

Thereby, a pattern structure 120 extending to the Y-axis may be formedon the plurality of the preliminary fin-type active patterns 102. Thepattern structure 120 may include the insulation pattern 112, the linepattern 114, the second mask pattern 110, and the spacer 116. Theinsulation pattern 112 may be a gate dielectric layer pattern of thefin-type field effect transistor. The line pattern 114 may perform as agate electrode of the fin-type field effect transistor. Thus the patternstructure 120 may also be referred to herein as a gate structure.

Referring to FIGS. 7a and 7b , a plurality of fin-type active patterns122 may be formed by partially etching the second region 102 b of theplurality of the preliminary fin-type active patterns 102.

The fin-type active pattern 122 may extend along the X-axis. Thefin-type active pattern 122 may have a first region 122 a having a firstthickness (e.g., vertical thickness, in a Z-direction) and a secondregion 122 b having a second thickness less than the first thickness.The first region 122 a of the fin-type active pattern 122 may overlappedthe line pattern 114, for example, in the Z-direction. The upper surfaceof the second region 122 b of the fin-type active pattern 122 may have alevel lower than or substantially equal to that of the upper surface ofthe device isolation pattern 106.

Referring to FIGS. 8a and 8b , a first preliminary impurity-dopedpattern 130 a and a second preliminary impurity-doped pattern 130 b maybe formed at both sides of the pattern structure, respectively. Thefirst preliminary impurity-doped pattern 130 a and the secondpreliminary impurity-doped pattern 130 b may be formed on the secondregion 122 b of the fin-type active pattern 122 by using a selectiveepitaxial growth process. A cross sectional view from the Y-axisdirection of the first and second preliminary impurity-doped patterns130 a and 130 b may have a rectangular shape, a hexagonal shape, apolygonal shape, or a circular shape. Horizontal widths (e.g., in theY-direction) of the first and second preliminary impurity-doped patterns130 a and 130 b may be greater than that of the fin-type active pattern122. The upper surfaces of the first and second preliminaryimpurity-doped patterns 130 a and 130 b may have a level lower than thatof upper surface of the pattern structure 120.

If the semiconductor device includes a fin-type PMOS transistor, thefirst and second preliminary impurity-doped patterns 130 a and 130 b mayhave a compressive stress. The compressive stress may be induced byinjecting a material having a lattice constant greater than that ofsilicon (Si), e.g., silicon germanium (SiGe) into the first and secondpreliminary impurity-doped patterns 130 a and 130 b.

If the semiconductor device includes a fin-type NMOS transistor, thefirst and second preliminary impurity-doped patterns 130 a and 130 b mayhave a tensile stress. The tensile stress may be induced by injecting amaterial having a lattice constant less than that of silicon (Si), e.g.,silicon carbide (SiC) into the first and second preliminaryimpurity-doped patterns 130 a and 130 b. Alternatively, the first andsecond preliminary impurity-doped patterns 130 a and 130 b may be formedof substantially the same material as the fin-type active pattern 122.In this case, the first and second preliminary impurity-doped patterns130 a and 130 b may be formed of silicon (Si).

Impurities may be injected into the first and second preliminaryimpurity-doped patterns 130 a and 130 b during the selective epitaxialgrowth process. For example, if the semiconductor device includes afin-type PMOS transistor, boron (B) may be injected into the first andsecond preliminary impurity-doped patterns 130 a and 130 b, for exampleby using an in-situ process. Carbon (C) may be further injected intothem to reduce diffusion of boron (B). Alternatively, if thesemiconductor device includes a fin-type NMOS transistor, arsenic (As)or phosphorus (P) may be injected into the first and second preliminaryimpurity-doped patterns 130 a and 130 b by using an in-situ process.

Referring to FIGS. 9a and 9b , alternatively, the impurities may beinjected into the first and second preliminary impurity-doped patterns130 a and 130 b by using a plasma doping process.

An exemplary plasma doping process will be specifically explained fromnow on. In one embodiment, the substrate 100 is loaded into a processchamber after forming the first and second preliminary impurity-dopedpatterns 130 a and 130 b using a selective epitaxial growth process asmentioned above referring to FIGS. 8a and 8b . Then, a source gas isinjected into the process chamber to perform the plasma doping process.

The source gas may include an impurity gas including an n-type dopant ora p-type dopant. The source gas may further include a dilution gas. Thedilution gas may include at least one selected from the group consistingof argon (Ar), neon (Ne), helium (He), hydrogen (H), Krypton (Kr), andXenon (Xe).

If the semiconductor device includes a fin-type PMOS transistor, theimpurity gas may include, for example, boron (B), boron hydride, and/orboron halide. The impurity gas may further include carbon (C), carbonhydride, and/or carbon halide.

If the semiconductor device includes a fin-type NMOS transistor, theimpurity gas may include, for example, arsenic (As) or phosphorus (P).For example, the impurity gas may include arsenic hydride and/or arsenichalide.

The impurities in the impurity gas may be ionized by a plasma induced inthe process chamber. The ionized impurities may be injected into thefirst and second preliminary impurity-doped patterns 130 a and 130 bwhen a direct current (DC) bias is induced to the substrate 100. Therebythe first and second preliminary impurity-doped patterns 130 a and 130 bmay be transformed to the first and second impurity-doped patterns 132 aand 132 b.

The first impurity-doped pattern 132 a may include an impurity-dopedregion having a uniform impurity concentration along certain surfaces(e.g., sidewalls) of the first region 122 a of the fin-type activeregion 122 (e.g., along a sidewall extending along the Y-Z plane). Theimpurity-doped region may have substantially the same thickness in anX-direction extending from the Y-Z surface of the sidewall of the firstregion 122 a.

The second impurity-doped pattern 132 b may also include animpurity-doped region having a uniform impurity concentration alongcertain surfaces of the first region 122 a and second region 122 b ofthe fin-type active region 122.

In one embodiment, the impurities may be vertically injected from theupper surface of the first and second impurity-doped patterns 132 a and132 b to the bottom of them. Therefore, the impurity concentration atthe upper surfaces of the first and second impurity-doped patterns 132 aand 132 b may be greater than those of their bottoms. Furthermore,contact resistances of contact plugs being electrically connected to thefirst and second impurity-doped patterns 132 a and 132 b may becomelower.

Referring to FIGS. 10a and 10b , the impurities injected in the firstand second impurity-doped patterns 132 a and 132 b may be diffused andactivated by performing an annealing process.

The annealing process may be performed, for example, at a temperature ofhigher than 900° C. The annealing process may include, for example, aspike annealing, a flash annealing, a laser annealing, and/or amicro-wave annealing.

The upper surfaces of the first and second impurity-doped patterns 132 aand 132 b may be damaged during the plasma doping process, and then thedamaged surfaces of the first and second impurity-doped patterns 132 aand 132 b may be cured by the annealing process.

In one embodiment, other impurities may be further injected into theupper surface of the first and second impurity-doped patterns 132 a and132 b by using a further injecting process. The further injectingprocess may include a beam-line-ion implantation process. In this case,the beam-line-ion implantation process may be performed for a very shorttime in order to protect further damage to the first and secondimpurity-doped patterns 132 a and 132 b.

As a result, a fin-type field effect transistor having the patternstructure 120 and the first and second impurity-doped patterns 132 a and132 b may be formed on the substrate 100. In this case, the insulationpattern 112 of the pattern structure 120 may be formed as a gatedielectric layer pattern and the line pattern 114 of the patternstructure 120 may be formed as a gate electrode of the fin-type fieldeffect transistor.

In one embodiment, the pattern structure 120 may be removed to form agate dielectric layer and a gate electrode layer by using a replacementprocess. Detail descriptions for the replacement process will follow.

FIGS. 11a through 20a are perspective views illustrating a method ofmanufacturing a semiconductor device according to an example embodimentof the inventive concepts. FIGS. 11b through 20b are cross-sectionalviews illustrating a method of manufacturing a semiconductor deviceaccording to an example embodiment of the inventive conceptscorresponding to line I-I′ of FIGS. 11a through 20 a.

Referring to FIGS. 11a and 11b , a fin-type active pattern 122, a deviceisolation pattern 106, and a pattern structure 120 may be formed on asubstrate 100. The fin-type active pattern 122, the device isolationpattern 106, and the pattern structure 120 may be formed respectively byusing substantially the same process as mentioned above referring toFIGS. 3a through 7a and FIGS. 3b through 7b . Therefore, detaileddescriptions about the methods of forming them will be omitted.

Impurities may be injected into the second region 122 b of the fin-typeactive region 122 which is not covered by the pattern structure 120using a plasma doping process. The impurities may be uniformly injectedinto the upper surface of the second region 122 b and the sidewall ofthe first region 122 a.

Before performing the doping process, a photoresist pattern 125 exposingthe second region 122 b of the fin-type active pattern 122 may befurther formed on the pattern structure 120. Alternatively, if a secondmask pattern 110 is formed on the line pattern 114, the forming of thephotoresist pattern 125 may be omitted.

The doping process will be described in detail as follows.

A substrate 100 having the photoresist pattern 125 may be loaded in aprocess chamber in which a plasma may be generated or induced. And then,a source gas may be injected into the process chamber.

The source gas may include an impurity gas. The source gas may furtherinclude a dilution gas. The dilution gas may comprise, for example, atleast one selected from the group consisting of argon (Ar), neon (Ne),helium (He), hydrogen (H), Krypton (Kr), and Xenon (Xe).

The impurity type of the source gas induced into the process chamber maybe variable in accordance with the type of the fin-type field effecttransistor, such as a PMOS or a NMOS transistor. Description for theimpurity type of the source gas may be omitted because it issubstantially the same as mentioned above referring to FIGS. 10a and 10b.

The impurities in the impurity gas may be ionized by inducing orgenerating plasma in the process chamber. The ionized impurities may beinjected into the second region 122 b of the fin-type active pattern 122when a direct current (DC) bias is induced to the substrate 100.

An impurity-doped region 202 may be formed at the upper surface of thesecond region 122 b of the fin-type active pattern 122 and at thesidewall of the first region 122 a of the fin-type active pattern 122 byperforming the plasma doping process. The impurity-doped region 202 mayinclude a first impurity-doped region 202 a formed at the upper surfaceof the second region 122 b and a second impurity-doped region 202 bformed at the sidewall of the first region 122 a. The firstimpurity-doped region 202 a and the second impurity-doped region 202 bmay have substantially the same thickness, which may be a uniformthickness.

The upper surfaces of the first and second regions 122 a and 122 b ofthe fin-type active pattern 122 may be less damaged if the impuritiesare injected by using a plasma doping process instead of thebeam-line-ion implantation process.

The plasma doping process may have an advantage of forming a shallowjunction having a highly doped region by controlling the bias voltageand the density of the plasma induced into the process chamber.

Referring to FIGS. 12a and 12b , the second impurity-doped region 202 bwhich is formed at the upper surface of the second region 122 b of thefin-type active pattern 122 may be selectively removed by using an etchprocess in order to reduce leakage current to the substrate 100. Theetch process may include, for example, an etch-back process. Therefore,only the second impurity-doped region 202 b on a sidewall of the firstregion 122 a may remain after the etch process.

Referring to FIGS. 13a and 13b , a knock-in process may be performed tothe second impurity-doped region 202 b of the first region 122 a.

The knock-in process may include injecting a knock-in gas into thesecond impurity-doped region 202 b of the first region 122 a. Theknock-in process may be helpful to distribute uniformly the impuritiesin the second impurity-doped region 202 b. The knock-in process may beperformed by using, for example, at least one selected from the groupconsisting of argon (Ar), neon (Ne), helium (He), hydrogen (H), Krypton(Kr), and Xenon (Xe). The knock-in process may also be referred to as auniform impurity distribution gas injecting process.

Referring to FIGS. 14a and 14b , a passivation layer 210 may be formedon the fin-type active pattern 122.

For example, if the impurities of the second impurity-doped region 202 binclude arsenic (As), arsenic may be evaporated before it is diffusedinside the second impurity-doped region 202 b because arsenic is asublimable material at a particular temperature. The passivation layer210 may keep arsenic (As) in the second impurity-doped region 202 bduring an annealing process that will be performed in a following step.The passivation layer 210 may be formed by using, for example, an oxygenplasma. In this case, the passivation layer 210 may include arsenicoxide (As_(x)O_(y)).

The knock-in process and the process for forming the passivation layer210 may be performed in-situ.

Referring to FIGS. 15a and 15b , the photoresist pattern 125 may beremoved. The photoresist pattern 125 may be removed, for example, byusing an aching and/or a strip process.

Referring to FIGS. 16a and 16b , a first annealing process may beperformed to diffuse the impurities disposed in the secondimpurity-doped region 202 b and the passivation layer 210. For example,the impurities may be diffused from the passivation layer 210 into thefirst and second regions 122 a and 122 b of the fin-type active pattern122 by performing the first annealing process.

The first annealing process may be performed at a first temperature. Thefirst temperature may have a range, for example, of about 500° C. toabout 700° C. The first annealing process may include at least oneselected, for example, from the group consisting of a rapid thermalanneal (RTA), a rapid thermal oxidation, a plasma annealing, and amicrowave annealing.

A portion of the fin-type active pattern 122 may be damaged by theplasma doping process and the damaged portion of the fin-type activepattern 122 may be cured by performing the first annealing process.

Referring to FIGS. 17a and 17b , a second annealing process may beperformed to activate the impurities disposed in the secondimpurity-doped region 202 b and the passivation layer 210. Theimpurities may be further diffused during the second annealing process.

The second annealing process may be performed in a second temperaturehigher than the first temperature. For example, the second temperaturemay have a range of greater than or equal to 900° C. The secondannealing process may include at least one selected from the groupconsisting of a spike annealing, a flash annealing, a laser annealing,and a microwave annealing.

Referring to FIGS. 18a and 18b , the passivation layer 210 may beremoved, for example, by using a wet etch process or a dry etch process.Thus, diffusion-based doped regions on sidewalls of the first region 122a and on a top surface of the second region 122 b may remain.

Referring to FIGS. 19a and 19b , a cleaning process may be performed toremove a byproduct formed during the plasma doping process and a residueof the passivation layer 210. The cleaning process may be performed, forexample, by using diluted hydrofluoric (HF) acid.

Referring to FIGS. 20a and 20b , a first impurity-doped pattern 220 aand a second impurity-doped pattern 220 b may be formed on the secondregion 122 b exposed at both sides of the pattern structure 120,respectively.

The first and second impurity-doped patterns 220 a and 220 b may beformed, for example, by a selective epitaxial growth process. The typeof the impurities may be variable according to the type of the fin-typefield effect transistor, e.g., NMOS or PMOS. Impurities may be injectedinto the first and second impurity-doped patterns 220 a and 220 b duringthe selective epitaxial growth process. Detailed descriptions aresubstantially the same to the descriptions as mentioned above referringto FIGS. 8a and 8b . Therefore, detailed descriptions about methods offorming the first and second impurity-doped patterns 220 a and 220 bwill be omitted.

The upper surfaces of the first and second impurity-doped patterns 220 aand 220 b may have a level higher than that of the fin-type activepattern 122. The upper surfaces of the first and second impurity-dopedpatterns 220 a and 220 b may have a level lower than that of the patternstructure 120. The widths of the first and second impurity-dopedpatterns 220 a and 220 b (e.g., in the Y-direction) may be greater thanthat of the fin-type active pattern 122.

The first and second impurity-doped patterns 220 a and 220 b may serveas a source/drain region of the fin-type field effect transistor.

Other impurities may be further injected into the first and secondimpurity-doped patterns 220 a and 220 b by using an injecting process.The injecting process may be performed by a beam-line-ion implantationprocess. In this case, the beam-line-ion implantation process may beperformed for a very short time in order to reduce further damage to thefirst and second impurity-doped patterns 220 a and 220 b.

As the result, the fin-type field effect transistor having the patternstructure 120 and the first and second impurity-doped patterns 220 a and220 b may be formed on the substrate 100. In this case, the insulationpattern 112 of the pattern structure 120 may serve as a gate dielectriclayer pattern. The line pattern 114 of the pattern structure 120 may beserve as a gate electrode of the fin-type field effect transistor.

Alternatively, the pattern structure 120 may be removed to form a gatedielectric layer and a gate electrode layer by using a replacementprocess. Detailed descriptions will be followed.

FIGS. 21a through 25a are perspective views illustrating a method ofmanufacturing a semiconductor device according to still another exampleembodiment of the inventive concepts. FIGS. 21b through 25b arecross-sectional views illustrating a method of manufacturing asemiconductor device according to still another example embodiment ofthe inventive concepts corresponding to line I-I′ of FIGS. 21a through25 a.

Referring to FIGS. 21a and 21b , a fin-type active pattern 122, a deviceisolation pattern 106, a pattern structure 120, and a first and secondimpurity-doped patterns 220 a and 220 b may be formed on a substrate100. The fin-type active pattern 122, the device isolation pattern 106,the pattern structure 120, and the first and the second impurity-dopedpattern 220 a and 220 b may be formed by substantially the same processas mentioned above referring to FIGS. 4a through 8a , FIGS. 4b through8b , FIGS. 12a through 20a , and FIGS. 12b through 20b . Therefore,detailed descriptions about the methods of forming them will be omitted.

An interlayer dielectric layer 230 may be formed on the surface of thesemiconductor device corresponding to FIGS. 20a and 20b . The interlayerdielectric layer 230 may include, for example, silicon oxide, siliconnitride, and/or silicon oxynitride. The interlayer dielectric layer maybe planarized to expose the upper surface of the pattern structure 120.

Referring to FIGS. 22a and 22b , the second mask pattern 110, the linepattern 114, and the dielectric pattern 112 of the pattern structure 120may be removed to form a trench 232 exposing the first region 122 a ofthe fin-type active pattern 122 and a portion of the device isolationpattern 106.

Referring to FIGS. 23a and 23b , a gate dielectric layer 234 may beconformally formed on the sidewall and at the bottom of the trench 232.The gate dielectric layer 234 may not fully fill the trench 232.

The gate dielectric layer 234 may include, for example, a high-kdielectric layer having a higher dielectric constant than that of asilicon oxide layer. The gate dielectric layer 234 may include at leastone selected, for example, from the group consisting of hafnium oxide,hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, tantalum oxide, titaniumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, or lead zinc niobate.

Referring to FIGS. 24a and 24b , a gate electrode layer 236 may beformed on the gate dielectric layer 234 disposed in the trench 232. Thegate electrode layer 236 may fill the trench 232.

The gate electrode layer 236 may have a multilayer structure. If thegate electrode layer 236 has a bilayer structure having a lower layer236 a and an upper layer 236 b, the lower layer 236 a may control thework function value of the gate electrode layer 236 and include at leastone selected from the group of titanium nitride (TiN), tantalum nitride(TaN), titanium carbide (TiC), and tantalum carbide (TaC). The upperlayer 236 b may include tungsten (W) and/or aluminum (Al).Alternatively, the gate electrode layer 236 may comprise silicon (Si)and/or silicon germanium (SiGe).

Referring to FIGS. 25a and 25b , the gate dielectric layer 234 and thegate electrode layer 236 may be planarized to expose the upper surfaceof the interlayer dielectric layer 230 and to form a gate dielectriclayer pattern 240 and a gate electrode 242.

From now on, descriptions about distribution of the impurityconcentration disposed in the first and second impurity-doped patterns220 a and 220 b will be disclosed in detail.

FIG. 26a is a cross-sectional view illustrating distribution of animpurity concentration disposed in an impurity-doped pattern of aconventional fin-type field effect transistor. FIG. 26b is across-sectional view illustrating distribution of an impurityconcentration disposed in an impurity-doped pattern of a fin-type fieldeffect transistor according to an example embodiment of the inventiveconcepts.

A first and a second impurity-doped pattern 30 a and 30 b of theconventional fin-type field effect transistor in FIG. 26a may be formedby a selective epitaxial growth process. Impurities may be injected intothe first and second impurity-doped patterns 30 a and 30 b by using anion-beam process. Reference numbers of 10, 20 a, 20 b, 40, 42 a, 42 b,42, 44, and 50 in FIG. 26a correspond to a substrate, a first region ofa fin-type active pattern, a second region of a fin-type active pattern,a gate dielectric layer, a lower gate electrode, an upper gateelectrode, a gate electrode, a spacer, and a pattern structure,respectively.

The first and second impurity-doped patterns 220 a and 220 b which aremanufactured according to an example embodiment of the inventiveconcepts may be formed by using a selective epitaxial growth processafter performing the plasma doping process as mentioned above referringto FIGS. 11a and 11b . Reference numbers of 100, 122 a, 122 b, 240, 242a, 242 b, 242, 244, and 250 in FIG. 26b correspond to a substrate, afirst region of a fin-type active pattern, a second region of a fin-typeactive pattern, a gate dielectric pattern, a lower gate electrode, anupper gate electrode, a gate electrode, a spacer, and a patternstructure, respectively. An interlayer dielectric layer 230 is alsoshown.

As shown in FIG. 26a , distributions of the impurity concentrationsdisposed in the upper portions of the first and second impurity-dopedpatterns 30 a and 30 b formed in the conventional fin-type field effecttransistor may have widths wider than those of distributions of theimpurity concentrations disposed in the lower portions of them,respectively. For example, the curved bands shown in FIG. 26A depictdifferent impurity concentrations, with light shades having the lowestconcentration compared to darker shades. As can be seen, the upperportion of the bands (extending in a mostly vertical direction at thetop of the impurity doped patterns 30 a and 30 b) are wider than thelower portion of the bands (extending in a mostly horizontal directionat an outer sidewall of the impurity doped patterns 30 a and 30 b). Assuch, the impurity distribution is not uniform.

On the contrary, as shown in FIG. 26b , distributions of the impurityconcentrations disposed in the upper portions of the first and secondimpurity-doped patterns 220 a and 220 b formed according to an exampleembodiment of the inventive concepts may have substantially same widthsto those disposed in the lower portions of them. Thus, distributions ofthese impurities are substantially uniform. Therefore, sheet resistancesof the upper portions of the first and second impurity-doped patterns220 a and 220 b adjacent to the first region 122 a of the fin-typeactive region 122 may be substantially the same as those of the lowerportions of them adjacent to the first region 122 a of the fin-typeactive region 122.

FIG. 27a is a schematic block diagram illustrating a memory cardincluding a semiconductor device according to an example embodiment ofthe inventive concepts.

Referring to FIG. 27a , a memory card 300 may include a memory device310. The memory device 310 may include at least one of the semiconductordevices according to the example embodiments of the inventive conceptsas mentioned above. The memory device 310 may include, for example, atleast one of a non-volatile memory device (e.g., a magnetic randomaccess memory device, a phase change random access memory device, etc),a dynamic random access memory (DRAM) device, and/or a static randomaccess memory (SRAM) device. The memory device may be included in asemiconductor device such as a semiconductor chip formed from a wafer,or a semiconductor package, or a package-on-package semiconductordevice. The memory card 300 may include a memory controller 320 thatcontrols data communication between a host and the memory device 310.

The memory controller 320 may include a central processing unit (CPU)324 that controls overall operations of the memory card 300. Inaddition, the memory controller 320 may include a SRAM device 322performed as an operation memory of the CPU 324. Moreover, the memorycontroller 320 may further include a host interface unit 326 and amemory interface unit 330. The host interface unit 326 may be configuredto include a data communication protocol between the memory card 300 andthe host. The memory interface unit 330 may connect the memorycontroller 320 to the memory device 310. The memory controller 320 mayfurther include an error check and correction such as an errorcorrection code (ECC) block 328. The ECC block 328 may detect andcorrect errors of data which are read out from the memory device 310.The memory card 300 may be used as, for example, a portable data storagecard. Alternatively, the memory card 300 may be realized as, forexample, solid state disks (SSD) which are used as hard disks ofcomputer systems.

FIG. 27b is a schematic block diagram illustrating an example ofinformation processing systems including a semiconductor deviceaccording to an example embodiment of the inventive concepts.

Referring to FIG. 27b , a memory system 410 including the semiconductordevice according to an embodiment of the inventive concept may beinstalled in an information process system 400 such as a mobile deviceor a desk top computer. The information process system 400 may include amodem 420, a central processing unit (CPU) 430, a random access memory(RAM) 440, and a user interface unit 450 that are electrically connectedto the memory system 410 through a system bus 460. Data processed by theCPU 430 or data inputted form the outside of memory system 410 may bestored in the memory system 410. Here, the memory system 410 may berealized as a solid state disk (SSD) device, and may include one or moresemiconductor devices such as described above in connection with FIGS.1-26. In this case, the information processing system 400 may stablystore massive data in the memory system 410. Additionally, as thereliability of the memory system 410 increases, the memory system 410may reduce a resource consumed for correcting errors. Even though notshown in the drawings, an application chipset, a camera image processor(CIS), and/or an input/output unit may further be provided in theinformation processing system 400.

The above-disclosed subject matter is to be considered illustrative andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the inventive concepts. Thus, the scope ofthe inventive concepts is to be determined by the broadest permissibleinterpretation of the following claims and their equivalents, and shallnot be restricted or limited by the foregoing detailed description.

What is claimed is:
 1. A semiconductor device, comprising: a fin-typeactive pattern protruding from a substrate and extending in a firstdirection, the fin-type active pattern including a first region having afirst vertical thickness and having sidewalls and a second region havinga second vertical thickness and an upper surface, the second verticalthickness less than the first vertical thickness; a pattern structurecrossing over the first region of the fin-type active pattern, thepattern structure extending in a second direction; and an impurity-dopedpattern formed on the upper surface of the second region and on a firstsidewall of the first region, wherein the impurity-doped pattern hasfirst impurity concentration at the upper surface of the second regionand has a second impurity concentration along the first sidewall of thefirst region, wherein the second impurity concentration is substantiallyuniform along the first sidewall.
 2. The semiconductor device of claim1, further comprising a device isolation pattern covering a lowerportion of the fin-type active pattern; and wherein an upper surface ofthe first region is higher than an upper surface of the device isolationpattern, and wherein the upper surface of the second region is lowerthan the upper surface of the device isolation pattern.
 3. Thesemiconductor device of claim 2, wherein an upper surface of theimpurity-doped pattern is higher than the upper surface of the deviceisolation pattern, but lower than the upper surface of the patternstructure.
 4. The semiconductor device of claim 1, wherein the secondimpurity concentration of the impurity-doped pattern along the firstsidewall of the first region is higher than the first impurityconcentration of the impurity-doped pattern at the upper surface of thesecond region.
 5. The semiconductor device of claim 1, wherein theimpurity doped pattern has a top surface and a bottom, and an impurityconcentration at the top surface of the impurity doped pattern is higherthan an impurity concentration at the bottom of the impurity dopedpattern.
 6. The semiconductor device of claim 1, wherein theimpurity-doped pattern has a substantially uniform thickness along theupper surface of the second region.
 7. A semiconductor device,comprising: a fin-type active pattern protruding from a substrate andextending in a first direction, the fin-type active pattern including afirst region having a first vertical thickness and having sidewalls anda second region having a second vertical thickness and an upper surface,the second vertical thickness less than the first vertical thickness; apattern structure crossing over the first region of the fin-type activepattern, the pattern structure extending in a second direction; and animpurity-doped pattern having a first impurity concentration on thesecond region of the fin-type active pattern and a second impurityconcentration along a first sidewall of the first region, wherein thesecond impurity concentration of the impurity-doped pattern along thefirst sidewall of the first region is substantially uniform, and whereinthe second impurity concentration is higher than an impurityconcentration at a bottom of the impurity-doped pattern.
 8. Thesemiconductor device of claim 7, further comprising a device isolationpattern covering a lower portion of the fin-type active pattern; andwherein an upper surface of the first region is higher than an uppersurface of the device isolation pattern, and wherein the upper surfaceof the second region is lower than the upper surface of the deviceisolation pattern.
 9. The semiconductor device of claim 8, wherein anupper surface of the impurity-doped pattern is higher than the uppersurface of the device isolation pattern, but lower than the uppersurface of the pattern structure.
 10. The semiconductor device of claim7, wherein the impurity-doped pattern has a top surface and a bottom,and an impurity concentration at the top surface of the impurity dopedpattern is higher than an impurity concentration at the bottom of theimpurity doped pattern.
 11. The semiconductor device of claim 7, whereinthe impurity-doped pattern has a substantially uniform thickness alongthe upper surface of the second region.
 12. A semiconductor device,comprising: a fin-type active pattern protruding from a substrate andextending in a first direction, an upper portion of the fin-type activepattern including a channel region and a pair of impurity-dopedpatterns; and a gate electrode crossing over the channel region andextending in a second direction, wherein the first and second directionsare parallel to a top surface of the substrate, wherein the channelregion is interposed between the pair of impurity-doped patterns suchthat the channel region and the pair of impurity-doped patterns arearranged along the first direction, wherein each of the pair ofimpurity-doped patterns has an impurity concentration along a sidewallof the channel region, the sidewall of the channel region being incontact with the each of the pair of impurity-doped patterns, andwherein the impurity concentration along the sidewall of the channelregion is substantially uniform.
 13. The semiconductor device of claim12, further comprising a device isolation pattern covering a lowerportion of the fin-type active pattern, wherein bottom surfaces of thepair of impurity-doped patterns are lower than an upper surface of thedevice isolation pattern.